The present invention is generally directed to the reduction of delay times seen by primary input signal lines employed in conjunction with shift register latch scan strings used in circuit test. More particularly, the present invention is directed to test circuitry employing shift register latch scan strings in which scan strings associated with primary inputs are segregated and supplied to their own signature register thus permitting simplified degating circuitry on the input side of shift register latches associated with primary inputs.
As the design of electronic integrated circuit chips and devices has progressed, more and more circuitry is being disposed in increasingly dense patterns and it is becomingly correspondingly more difficult to test such circuits. One methodology for performing chip test is described in U.S. Pat. No. 4,071,902 issued to Edward Eichelberger, et al. on Jan. 31, 1978 and assigned to the same assignee as the present invention. This patent describes the basic features of the level sensitive scan design (LSSD) system for circuit test. The circuits generally considered therein include digital circuits having logic and memory functions that are used in the design and construction of digital signal processing and information handling systems and machines. Likewise here, integrated circuit devices of interest typically possess blocks of combinatorial logic whose outputs are supplied to certain memory elements. In particular, in an LSSD system the memory elements or circuits comprise shift register latches (SRLs). During test mode, these shift register latches can be logically reconfigured to operate as a shift register which is capable of storing logical output results and of moving or shifting these results into a storage register for comparison and analysis with known results.
In addition to providing circuits of greater complexity, the other significant purpose in reducing circuit size is to produce circuits which operate faster. This is accomplished as a by-product of increased circuit densification simply as a result of the fact that circuits are now close together and signals experience smaller delays from one circuit or gate to the next. Accordingly, it is seen that it is very desirable to eliminate circuit delays wherever possible. The goals of increased speed and increased circuit density are in conflict though with the need to produce chip devices which are fabricated flawlessly and operate perfectly. The goals of increased speed and denser circuit layout are also at least partially in conflict with the desire to provide built-in diagnostic circuitry which itself consumes valuable space (real estate) on a circuit chip.
During normal functioning of the integrated circuit device, information signals are stored in the memory elements (shift register latches) by the operation of one or more system clocks, and are thence supplied to blocks of combinatorial logic circuits whose outputs are again stored in memory elements by operation of one or more system clocks. Subsequently, these information signals are supplied to other combinatorial logic blocks. However, during test operations, test patterns are shifted into these memory elements using the shift register mode of operation using separate shifting clocks. Normal system clocks then capture the responses to these patterns in the memory elements, and these responses are in turn shifted into a tester storage register for comparison with known results.
As a further aid to testing of the integrated circuit device, a boundary-scan method is used in which a memory element (SRL) is placed adjacent to each input/output pin of the device so that signals on the boundary can be controlled and observed using shifting operations. This represents a dramatic simplification of the test equipment in that it is no longer necessary to make physical contact with the actual input/output pin. Additionally, the boundary-scan methodology permits a test of the wires that connect devices within a computer system, by supplying signals to the output SRLs of all devices and sensing such signals at SRL's connected to their inputs. During normal functioning of the device, information signals are stored in these boundary SRLs using one or more system clocks.
One further aid to device and system testing is a method called self-test. A methodology for self-testing in an LSSD environment is described in U.S. Pat. No. 4,503,537 issued to William McAnney, a co-inventor herein, on Mar. 5, 1985 and assigned to the same assignee as the present invention. In accordance with one aspect of this method, the scan outputs of the shift register strings are fed into a so-called multiple input signature register or MISR. During test, the signals captured into the SRLs are "compressed" within the MISR to form a resultant or signature at the end of test that can be compared with the expected or good signature for a pass/fail decision. It is important to note that the integrated circuit device may be self-tested as a stand-alone device, and may also be self-tested when incorporated within the construction of a digital processing system or machine.
In the present invention, attention is specifically focused on the boundary-scan SRLs that are associated with primary inputs to the device. Primary inputs (PIs) are physical pins or terminals through which the outside world supplies information to the device, as opposed to primary outputs (POs) through which the device supplies information to the outside world. During test operations normal system clocks are used to capture test responses into the memory elements or SRLs. These same clocks functionally affect the PI boundary-scan SRLs and, unless controlled, will load into those latches the values on the physical PI pin. This can create either of two problems: First, when the integrated circuit is being tested as a stand-alone device, these PI pins are not driven by the tester, and their values are generally unknown. If self-test is being used, these unknown values or "X" states can be loaded into their SRLs and can contaminate the self-test signature and invalidate the test. Second, if the integrated circuit has been incorporated in the construction of a digital system or machine, self-test of the circuit will load unknown off-circuit values or "X" states to the SRLs and again contaminate the signature.
One approach to avoiding "X" states is to degate all primary input pins from their SRLs during either stand-alone or system level test. This degating circuitry can, by its mere presence, adversely affect the basic machine cycle time. A second approach is to degate the system clocks to the primary input SRLs during test. Again, a similar adverse effect on system performance can occur.